01
Tinker CPU
Depth almost nobody at this stage has
- The problem
- Build a 64-bit out-of-order processor in SystemVerilog — dual-issue, register renaming, reservation stations, a reorder buffer, branch prediction, and a pipelined FPU.
- The constraint that made it hard
- DRAFT Almost nobody building a CPU at this level attempts real out-of-order execution; the honest reason is verification, not RTL. Register renaming has to be correct against every WAW/WAR hazard combination, and a broken interaction between the reservation stations and the reorder buffer doesn’t show up as a compile error — it shows up as a wrong answer three instructions later.
- What was chosen — and against
- DRAFT Chose a Tomasulo-style design (reservation stations + a reorder buffer) over a simpler in-order scoreboard. Against: that would have shipped faster and been easier to verify, but it wouldn’t have proven anything about real superscalar execution — the whole point was building the version that’s actually hard.
- What I’d do differently
- DRAFT Write the randomized instruction-sequence verification harness before the FPU pipeline, not after. The FPU came first because it felt like the fun part; the hazard bugs that took longest to find were always in renaming, and a fuzzer would have caught them earlier.